Academic Journal
Q1IEEE Open Journal of the Solid-State Circuits Society
About IEEE Open Journal of the Solid-State Circuits Society
IEEE Open Journal of the Solid-State Circuits Society is a scholarly journal published by Institute of Electrical and Electronics Engineers Inc.. SCImago 2025 lists it in Q1, with an SJR of 1.759 and H-index of 18.
Coverage: 2021-2026. Research categories: Electrical and Electronic Engineering (Q1); Electronic, Optical and Magnetic Materials (Q1).
Open-access policies and author information
Reported in the official DOAJ public CSV snapshot (2026-09-01), downloaded 2026-10-03. Record updated 2026-03-12. This snapshot does not establish today’s listing status or fee quotation.
Publisher policy links recorded by DOAJ
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Source-backed journal facts
Topics in published research
Analog and Mixed-Signal Circuit Design; Radio Frequency Integrated Circuit Design; Advancements in PLL and VCO Technologies; Advancements in Semiconductor Devices and Circuit Design; Low-power high-performance VLSI design; Advanced Memory and Neural Computing.
OpenAlex classifies topics from published works. These topics are not the publisher’s official aims and scope.
Source: OpenAlex source record. Retrieved 2026-10-03. Source record updated 2026-10-02. OpenAlex metrics are different from SCImago metrics and the Clarivate Journal Impact Factor.
Journal Metrics
Quartile, SJR and the listed SCImago H-index use the 2025 imported SCImago dataset. A quartile may vary by subject category. Values without a source or reporting year are unverified historical entries. Verify the current Journal Impact Factor with Clarivate or the publisher before using it.
Aims & Scope
The publisher’s official aims and scope have not yet been verified for this profile. Use the journal website to check subject fit and accepted article types before submitting.
Recent Research Articles
Latest publications matched automatically by ISSN.
A Resonant Dual-Path Interleaved DC-DC Converter With Reduced Input RMS Current, 0.5 W/mm 2 Power Density and 91.6% Peak Efficiency
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2026 · DOI: 10.1109/ojsscs.2026.3709735Robust and Scalable Cell-Based 65-nm CMOS RO-PUF Implementation
P. Ortega-Castro, E. Camacho-Ruiz, J. M. Mora-Gutiérrez, P. Brox et al.
2026 · DOI: 10.1109/ojsscs.2026.3689804A 40-nm 30.69-TOPS/W Weight Sharing FC-DNN Engine for Audio Processing Using CAM-Based In-Memory Search and DIMC-Based Approximate Computing
Jinn-Shyan Wang, Tay-Jyi Lin, Je Li, Yuen-Cheng Cheng et al.
2026 · DOI: 10.1109/ojsscs.2026.3696286An Overview of Time-Interleaved Noise-Shaping ADCs: Fundamentals, Challenges, and Prospects
Yuekai Liu, Ziqiang Cai, Yan Liu, Liang Qi et al.
2026 · DOI: 10.1109/ojsscs.2026.3665854A 12-b 3-GS/s Pipelined ADC With Piecewise-Linear Gain Nonlinearity Calibration
Mingyang Gu, Yi Zhong, Lu Jie, Nan Sun et al.
2026 · DOI: 10.1109/ojsscs.2026.3656850A Highly Reliable PUF Based on Reconfigurable Sub-Threshold Voltage Divider in 65-nm CMOS
M. Vatalaro, R. De Rose, V. Maccaronio, F. Crupi et al.
2026 · DOI: 10.1109/ojsscs.2026.3677765New Associate Editors
Woogeun Rhee
2026 · DOI: 10.1109/ojsscs.2026.3652568Cryogenic CMOS RF AWGs for Qubit Control
Sudipto Chakraborty, Marcel Kossel, Matthias Brändli, Pier-Andrea Francese et al.
2026 · DOI: 10.1109/ojsscs.2026.3660196A Pipelined Incremental ΔΣ ADC With Residue Harvesting and Noise Penalty Mitigation
Shih-Che Kuo, Chia-Hung Chen
2026 · DOI: 10.1109/ojsscs.2026.3664789A 40-GHz 2-D Scalable Quasi-Rotary Traveling-Wave Oscillator Array with Impedance-Discontinuity Compensation for Continuous Traveling-Wave Propagation
Chen Yu, Liang Wu
2026 · DOI: 10.1109/ojsscs.2026.3734124ADiP: Adaptive-Precision Systolic Array for Matrix Multiplication Acceleration
Ahmed J. Abdelmaksoud, Cristian Sestito, Shiwei Wang, Themis Prodromakis et al.
2026 · DOI: 10.1109/ojsscs.2026.3684844Non-Volatile Digital Compute-in-Memory Macro with Ferroelectric FET-based Voltage Divider Weight Cells Featuring Power-Gating
Matthew Chen, Vaidehi Garg, Jianwei Jia, Jay Sonawane et al.
2026 · DOI: 10.1109/ojsscs.2026.3678878Capacitance-to-Digital Converters: Recent Advances and Evolving Trends From Circuit-Level Performances to System Requirements
Donghyun Youn, Gichan Yun, Yoontae Jung, Hoyong Seong et al.
2026 · DOI: 10.1109/ojsscs.2026.3686096Buckbeak: A 1.2 TFLOPS/W Reconfigurable Vector/Scalar RISC-V Processor for Precision Scalable Near-Sensor Computing in 22-nm FDSOI Technology
Marco Bertuletti, Amirhossein Kiamarzi, Mattia Sinigaglia, Gianmarco Ottavi et al.
2026 · DOI: 10.1109/ojsscs.2026.3695835High-Order Continuously Scalable-Conversion-Ratio Switched-Capacitor Converters
Zhiyuan Zhang, Yuan Wang, Rui P. Martins, Sijun Du et al.
2026 · DOI: 10.1109/ojsscs.2026.3715124A Wired-Logic and Near-Memory Hybrid Processor for General-Purpose Audio Inference Using a Self-Supervised Encoder
Jaewon Shin, Kenji Kobayashi, Kota Shiba, Jiawei Yu et al.
2026 · DOI: 10.1109/ojsscs.2026.3703368Laser-Induced Fault Injection on Trivium Stream Cipher ASICs: A Feasible Attack for Key Recovery
J. M. Mora-Gutierrez, F. E. Potestad-Ordonez, C.J. Jimenez-Fernandez
2026 · DOI: 10.1109/ojsscs.2026.3724800Fully Passive Techniques for Reducing Supply Sensitivity in LC Oscillators
Renxu Yang, Robert Bogdan Staszewski, Masoud Babaie, Kai Kang et al.
2026 · DOI: 10.1109/ojsscs.2026.3723352A 2.5D Distributed Group Vector Systolic Accelerator for Tensor Compression based MLA and MOE LLMs
Sixiao Huang, Xu Shi, Xiaohan Pei, Kai Li et al.
2026 · DOI: 10.1109/ojsscs.2026.3705711A 18.1TFLOPs/W Transformer Accelerator with Fine-Grained Per-Query Latency and Power Management in 12-nm FinFET
Thierry Tambe, David Kong, Joshua Park, Gage Hills et al.
2026 · DOI: 10.1109/ojsscs.2026.3674438Reviews
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Version History
September 25, 2026 at 7:19 am
September 25, 2026