Academic Journal
Q2Integration
About Integration
Integration is a scholarly journal published by Elsevier B.V.. SCImago 2025 lists it in Q2, with an SJR of 0.479 and H-index of 53.
Coverage: 1983-2026. Research categories: Electrical and Electronic Engineering (Q2); Hardware and Architecture (Q2); Software (Q2).
Source-backed journal facts
Topics in published research
Low-power high-performance VLSI design; VLSI and FPGA Design Techniques; VLSI and Analog Circuit Testing; Analog and Mixed-Signal Circuit Design; Interconnection Networks and Systems; Advancements in Semiconductor Devices and Circuit Design.
OpenAlex classifies topics from published works. These topics are not the publisher’s official aims and scope.
Reported open-access list prices
2,230.00 USD; 2,030.00 EUR; 1,790.00 GBP; 263,100.00 JPY
APC list prices reported by OpenAlex, which obtains this information from DOAJ. Confirm current charges, taxes, waivers and eligibility with the publisher; this is not a fee quotation.
Source: OpenAlex source record. Retrieved 2026-10-03. Source record updated 2026-10-02. OpenAlex metrics are different from SCImago metrics and the Clarivate Journal Impact Factor.
Journal Metrics
Quartile, SJR and the listed SCImago H-index use the 2025 imported SCImago dataset. A quartile may vary by subject category. Values without a source or reporting year are unverified historical entries. Verify the current Journal Impact Factor with Clarivate or the publisher before using it.
Aims & Scope
The publisher’s official aims and scope have not yet been verified for this profile. Use the journal website to check subject fit and accepted article types before submitting.
Recent Research Articles
Latest publications matched automatically by ISSN.
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Billa Nazma, M. Chennakesavulu
2027-01 · DOI: 10.1016/j.vlsi.2026.102887An error-aware design methodology for hardware-efficient approximate square root circuits
Merin Loukrakpam, Ruskin Potsangbam, Priyanka Thingom
2027-01 · DOI: 10.1016/j.vlsi.2026.102865Knowledge-augmented robust analog circuit sizing under PVT variations via multi-scenario optimization
Huaiyu Zhao, Chunliang Zhao, Chengzhi Jiang, Dunwei Gong et al.
2027-01 · DOI: 10.1016/j.vlsi.2026.102880A 1.7-GHz bulk-voltage-tunable regulated cascode current mirror at 90-nm CMOS technology
Uma Sharma, Pritty, Richa Srivastava, Pravesh et al.
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Yadi Lin, Wendi Lin
2027-01 · DOI: 10.1016/j.vlsi.2026.102888A broadband 13–25 GHz driver amplifier using high-order matching networks in 40-nm CMOS
Xuanzhang He, Liyan Yu, Junjie Cao, Junyan Leng et al.
2027-01 · DOI: 10.1016/j.vlsi.2026.102860Robust memristive neural networks with efficient in-situ training
Santlal Prajapati, Manobendra Nath Mondal, Susmita Sur-Kolay
2027-01 · DOI: 10.1016/j.vlsi.2026.102897Soft fault diagnosis and fault-tolerant control of SIDO buck converter based on adaptive finite-time observer
Minggui Mo, Rong Zhang, Mei Chen
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Zijian Ding, Yang Zou, Yizhou Sun, Jason Cong et al.
2027-01 · DOI: 10.1016/j.vlsi.2026.102878LOA-RF: An intelligent fault classification framework for 16-bit charge scaling DACs under process and environmental variations
L. Jubair Ahmed, V. Govindaraj, C. Ezhilazhagan, D. Preethi et al.
2027-01 · DOI: 10.1016/j.vlsi.2026.102867Reviews
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October 4, 2026 at 9:19 pm
October 2, 2026