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14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI

Bert Moons, Roel Uytterhoeven, Wim Dehaene, Marian Verhelst

📖 Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 📅 2017-02-01 🔗 DOI: 10.1109/isscc.2017.7870353

📄 Abstract

ConvNets, or Convolutional Neural Networks (CNN), are state-of-the-art classification algorithms, achieving near-human performance in visual recognition [1]. New trends such as augmented reality demand always-on visual processing in wearable devices. Yet, advanced ConvNets achieving high recognition rates are too expensive in terms of energy as they require substantial data movement and billions of convolution computations. Today, state-of-the-art mobile GPU’s and ConvNet accelerator ASICs [2][3] only demonstrate energy-efficiencies of 10’s to several 100’s GOPS/W, which is one order of magnitude below requirements for always-on applications. This paper introduces the concept of hierarchical recognition processing, combined with the Envision platform: an energy-scalable ConvNet processor achieving efficiencies up to 10TOPS/W, while maintaining recognition rate and throughput. Envision hereby enables always-on visual recognition in wearable devices.

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