SCHOLARLY PUBLICATION

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS

📖 Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 📅 2010-02-01 🔗 DOI: 10.1109/isscc.2010.5434077

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📄 Abstract

A 567 mm2processor on 45 nm CMOS integrates 48 IA-32 cores and 4 DDR3 channels in a 6×4 2D-mesh network. Cores communicate through message passing using 384 KB of on-die shared memory. Fine-grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. As performance scales, the processor dissipates between 25 W and 125 W.

ℹ️ Publication Details

Journal: Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Published: 2010-02-01
DOI: 10.1109/isscc.2010.5434077
OpenAlex: W1974420955
Access: Via publisher

📋 Cite This Paper

Jason Howard, Saurabh Dighe, Yatin Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David R. Jenkins, Howard Wilson, Nitin Borkar, G. Schrom, Fabrice Paillet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Y. Borkar, Vivek K. De, Rob Van der Wijngaart, Timothy G. Mattson (2010). A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference. https://doi.org/10.1109/isscc.2010.5434077

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